1. Field of the Invention
The present invention generally relates to dynamic random access memories (DRAMs) and, more particularly, to a technique which increases the availability of a DRAM by accessing non-refreshing portions of the DRAM.
2. Background Description
The storage cells of a dynamic random access memory (DRAM) need to be refreshed typically every 64 milliseconds (ms) to maintain data stored therein. In conventional DRAMs, an autorefresh cycle accomplishes refresh of a single row of storage cells. An Internal counter increments on every autorefresh cycle to refresh all the rows in the DRAM array. An AUTOREFRESH command, as set forth in standard JC-42.3-94-126, item #612, approved by the Joint Electronic Device Engineering Council (JEDEC) in January 1995, is issued to initiate this cycle. To issue this command, all banks of the DRAM have to be in an idle state, or at least in a state where an ACTIVATE command would be legal (i.e., not in a power down state). Thus, to retain the information stored in the DRAM under current standards, an AUTOREFRESH command has to be issued, for example, 4092 times every 64 ms. The need for refresh causes the DRAM to be unavailable to the system for some period of time. For example, the autorefresh cycle for the example given can be performed in 15.6 microseconds (xcexcs), or a burst of 4092 autorefresh cycles every 64 ms. While the DRAM is being refreshed during the autorefresh cycle, it cannot be accessed by the processor. If the processor attempts to access the memory system during an autorefresh cycle, one or more wait states will occur. This is a potential source of performance degradation in computer systems, particularly with the newer high density memory chips.
It is therefore an object of the present invention to provide a technique which will allow DRAMs in a computer memory system to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system.
According to the invention, a DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. For example, if Bank 1 is idle, Banks 2 and 3 are precharging and Bank 0 is active and currently in a burst read operation, an AUTOREFRESH command can be issued on Bank 1 only, while the other banks continue to perform their tasks. The decoding is done much in the same way as coding in the precharge command (as in the JEDEC standard), where A11 decides whether the refresh is to be performed undecoded or decoded. In the latter case, the bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry also makes sure that every bank of the DRAM gets a refresh command often enough to retain information.